Directory structure:

1. dc -directory for logic synthesis
2. fm - directory for formal verification
3. hercules - directory for post-layout DRC,LVS checks
4. icc - directory for physical synthesis
5. models - directory for technology files for standard cells in Liberty syntax
6. ptpx - directory for power analysis
7. ref - all needed information for physical synthesis
8. src - RTL directory
9. sta - directory for static timing analysis
10. starrc - directory for post-layout parasitic extraction
11. tmax - directory for ATPG generation
12. vcs -directory for functional verification
13. verilog -  verilog codes of library cells

Design process:

Step 1: Move to directory ./dc for logical synthesis. Follow the steps written in
        ./dc/README.dc file 
Step 2: Move to directory ./fm for formal verification.Follow the steps written in
        ./fm/README.fm file 
Step 3: Move to directory ./icc for physical synthesis.Follow the steps written in
        ./icc/README.icc file 
Step 4: Move to directory ./hercules for post-layout DRC,LVS checks. Follow the steps written in
        ./hercules/README.hercules file 
Step 5: Move to directory ./sta for static timing analysis. Follow the steps written in
        ./sta/README.sta file 
Step 6: Move to directory ./ptpx for power analysis. Follow the steps written in
        ./ptpx/README.ptpx file 
Step 7: Move to directory ./tmax for ATPG generation.Follow the steps written in
        ./tmax/README.tmax file 
Step 8: Move to directory ./vcs for functional verification. Follow the steps written in
        ./vcs/README.vcs file 
Step 9: Move to directory ./starrc for post-layout parasitics extraction. Follow the steps written in
        ./starrc/README.starrc file 		
	
Several design steps can be repeated where necessary.
